The present invention relates to an image reproduction interface which is disposed between a display device and a central processing unit (hereinafter abbreviated as CPU) producing a multiplicity of code signals corresponding to image elements, for transferring the code signal from the CPU to the display device.
An interface known in the art for use in connection with a display device for image reproduction is commonly provided with a video storage in the form of a random-access memory for temporarily storing code signals which are generated from a central processing unit and represent respective multiple image elements to be reproduced on the display device. The stored code signals are successively fed to the display device in a predetermined order, so that an image consisting of multiple image elements corresponding to the code signals stored in the random-access video memory are viewed on the screen of the display device. More specifically, each group of individual code signals corresponding to an image on one screen or a line of image elements are read out in sequence from the random-access memory at a predetermined rate, i.e., at a predetermined interval at which the individual image elements are reproduced. Therefore, it is commonly practiced that the storage or writing of the code signals into the video memory is effected during blanking periods of the display device so that the storage period (write time) will not overlap with the read-out period (read time). In a case where the display device is a cathode-ray tube (CRT), for example, the blanking time is a portion of each retrace interval of vertical or horizontal scanning signals, during which portion an electron beam of the CRT is cut off and no image reproduction takes place.
In such an arrangement, however, the read time during which the code signals are called for from the video memory is generally so adapted to be considerably longer than the blanking time. In a cathode-ray tube, for example, the read time for feeding the code signals from the video memory to the CRT is usually about five times as long as the blanking time. Accordingly, the writing time of the CPU for storage of the code signals in the memory is limited, whereby the CPU has to spend a lot of time in transferring to the memory a large number of code signals which have been stored in the CPU to reproduce an entire image on the next screen, e.g., full text of the next page of a document. This will obviously result in decrease in the rate of image reproduction.
To eliminate or alleviate the above indicated drawbacks experienced in the art, it has been proposed to allow the CPU to write or store the code signals into the random-access video memory prior to the delivery of the stored information from the video memory to the display device. In this instance wherein the priority is given to the storage operation, however, the delivery of the code signals to the display device is interrupted, and as a result the display screen will flicker. As an alternative solution to the above problem, it has also been attempted to adopt a multi-processor system wherein another processing unit is used to serve as a control unit exclusively for the display device. While this solution is successful in maintaining a sufficiently high image reproduction rate and preventing the flickering phenomenon of the screen image, it requires a complicated control arrangement.